In designing semiconductor devices, design layouts for the devices can be optimized by optimizing certain features of the layout, such as the dimensions of the active region. However, optimization of the dimensions of the active region can be different based on whether the design layout is for a planar semiconductor design layout or a FinFET semiconductor design layout. For example, a planar transistor does not have a transistor width restriction. However, a FinFET width must be an integer multiple of a fin parameter (e.g., fin pitch), such as an integer multiple of 48 nm. Yet, a planar design can be migrated to a FinFET design to take advantage of FinFET performance improvements. Design transitioning efforts are, however, required to be minimal because of time to market and other constraints. Such constraints require minimal changes in the layout and schematics from planar to FinFET designs.
Making a transistor compatible in both semiconductor designs requires a transistor width quantization in the planar design to be compatible with the fin pitch (e.g., direct finification). Yet, direct finification leads to a reduction in the size of the active region for the planar design and, therefore, degrades performance of the planar transistor.
A need, therefore, exists for methodology and an apparatus enabling an optimal planar design without losing performance because of quantization while also maintaining an optimal FinFET design.